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hyb25d256[800/160]bt(l) -[5/5a] 256mbit double data rata sdram preliminary ddr400 data sheet addendum jan. 2003, v0.9 2003-01-10, v0.9 page 1 of 29 features ? double data rate architecture: two data transfers per clock cycle ? bidirectional data strobe (dqs) is transmitted and received with data, to be used in capturing data at the receiver ? dqs is edge-aligned with data for reads and is center-aligned with data for writes ? differential clock inputs (ck and ck ) ? four internal banks for concurrent operation ? data mask (dm) for write data ? dll aligns dq and dqs transitions with ck transitions ? commands entered on each positive ck edge; data and data mask referenced to both edges of dqs ? burst lengths: 2, 4, or 8 ? cas latency: (1.5), 2, 2.5, (3) ? auto precharge option for each burst access ? auto refresh and self refresh modes ?7.8 s maximum average periodic refresh interval (8k refresh) ? 2.5v (sstl_2 compatible) i/o ?v ddq = 2.6v 0.1v / v dd = 2.6v 0.1v ? tsop66 package description the 256mb ddr sdram is a high-speed cmos, dynamic random-access memory containing 268,435,456 bits. it is internally configured as a quad-bank dram. the 256mb ddr sdram uses a double-data-rate archi- tecture to achieve high-speed operation. the double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the 256mb ddr sdram effectively consists of a sin- gle 2n -bit wide, one clock cycle data transfer at the inter- nal dram core and two corresponding n-bit wide, one- half-clock-cycle data transfers at the i/o pins. a bidirectional data strobe (dqs) is transmitted externally, along with data, for use in data capture at the receiver. dqs is a strobe transmitted by the ddr sdram during reads and by the memory controller during writes. dqs is edge-aligned with data for reads and center-aligned with data for writes. the 256mb ddr sdram operates from a differential clock (ck and ck ; the crossing of ck going high and ck going low is referred to as the positive edge of ck). commands (address and control signals) are registered at every positive edge of ck. input data is registered on both edges of dqs, and output data is referenced to both edges of dqs, as well as to both edges of ck. read and write accesses to the ddr sdram are burst oriented; accesses start at a selected location and con- tinue for a programmed number of locations in a pro- grammed sequence. accesses begin with the registration of an active command, which is then followed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be accessed. the address bits registered coinci- dent with the read or write command are used to select the bank and the starting column location for the burst access. the ddr sdram provides for programmable read or write burst lengths of 2, 4 or 8 locations. an auto pre- charge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. as with standard sdrams, the pipelined, multibank archi- tecture of ddr sdrams allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. an auto refresh mode is provided along with a power-sav- ing power-down mode. all inputs are compatible with the jedec standard for sstl_2. all outputs are sstl_2, class ii compatible. note: the functionality described and the timing specifi- cations included in this data sheet are for the dll enabled mode of operation. cas latency and clock frequency cas latency maximum operating frequency (mhz) ddr400b -5 ddr400a -5a 2 133 133 2.5 166 200 3 200 200
hyb25d256[800/160]bt(l)-[5/5a] 256mbit double data rata sdram preliminary ddr400 data sheet addendum page 2 of 29 2003-01-10, v0.9 ordering information part number a a. hyb: designator for memory components 25d: ddr-i sdrams at vddq=2.5v 256: 256mb density 400/800/160: product variations x4, x8 and x16 b: die revision b c/t: package type fbga and tsop l: low power version (optional) - these components are spec ifically selected for low idd6 self refresh currents -5: speed grade - see table org. cas-rcd-rp latencies clock (mhz) cas-rcd-rp latencies clock (mhz) cas-rcd-rp latencies clock (mhz) speed package hyb25d256800bt(l)-5a x8 3-3-3 200 2.5-3-3 200 2-3-3 133 ddr400a 66 pin tsop-ii hyb25d256160bt(l)-5a x16 hyb25d256800bt(l)-5 x8 166 ddr400b hyb25d256160bt(l)-5 x16
hyb25d256[800/160]bt(l)-[5/5a] 256mbit double data rata sdram preliminary ddr400 data sheet addendum 2003-01-10, v0.9 page 3 of 29 pin configuration (tsop66) 1 2 3 4 5 6 9 10 11 12 13 14 7 8 15 16 17 18 19 20 21 22 66 65 64 63 62 61 58 57 56 55 54 53 60 59 52 51 50 49 48 47 46 45 23 24 25 44 43 42 26 27 41 40 28 29 30 31 32 33 39 38 37 36 35 34 v dd dq0 v ddq nc dq1 v ssq v ddq nc dq3 v ssq nc nc nc dq2 v ddq nc nc v dd nc nc we cas ras cs nc ba0 ba1 v ss dq7 v ssq nc dq6 v ddq v ssq nc dq4 v ddq nc nc nc dq5 v ssq dqs nc v ref v ss dm ck ck cke nc a12 a11 a9 v dd nc v ddq nc dq0 v ssq v ddq nc dq1 v ssq nc nc nc nc v ddq nc nc v dd nc nc we cas ras cs nc ba0 ba1 v ss nc v ssq nc dq3 v ddq v ssq nc dq2 v ddq nc nc nc nc v ssq dqs nc v ref v ss dm ck ck cke nc a12 a11 a9 a10/ap a0 a1 a2 a3 v dd a10/ap a0 a1 a2 a3 v dd a8 a7 a6 a5 a4 v ss a8 a7 a6 a5 a4 v ss 64mb x 4 32mb x 8 v dd dq0 v ddq dq1 dq2 v ssq v ddq dq5 dq6 v ssq dq7 nc dq3 dq4 v ddq ldqs nc v dd nc ldm we cas ras cs nc ba0 ba1 a10/ap a0 a1 a2 a3 v dd 16mb x 16 v ss dq15 v ssq dq14 dq13 v ddq v ssq dq10 dq9 v ddq dq8 nc dq12 dq11 v ssq udqs nc v ref v ss udm ck ck cke nc a12 a11 a9 a8 a7 a6 a5 a4 v ss
hyb25d256[800/160]bt(l)-[5/5a] 256mbit double data rata sdram preliminary ddr400 data sheet addendum page 4 of 29 2003-01-10, v0.9 input/output functi onal description symbol type function ck, ck input clock: ck and ck are differential clock inputs. all address and control input signals are sam- pled on the crossing of the positive edge of ck and negative edge of ck . output (read) data is referenced to the crossings of ck and ck (both directions of crossing). cke input clock enable: cke high activates, and cke low deactivates, internal clock signals and device input buffers and output drivers. taki ng cke low provides precharge power-down and self refresh operation (all banks idle), or active power-down (row active in any bank). cke is synchronous for power down entry and ex it, and for self refresh entry. cke is asyn- chronous for self refresh exit. cke must be maintained high throughout read and write accesses. input buffers, excluding ck, ck and cke are disabled during power-down. input buffers, excluding cke, are disabled during self refresh. cs input chip select: all commands are masked when cs is registered high. cs provides for exter- nal bank selection on systems with multiple banks. cs is considered part of the command code. the standard pinout includes one cs pin. ras , cas , we input command inputs: ras , cas and we (along with cs ) define the command being entered. dm input input data mask: dm is an input mask signal for write data. input data is masked when dm is sampled high coincident with that input data during a write access. dm is sampled on both edges of dqs. although dm pins are input only, the dm loading matches the dq and dqs loading. ba0, ba1 input bank address inputs: ba0 and ba1 define to which bank an active, read, write or pre- charge command is being applied. ba0 and ba1 al so determines if the mode register or extended mode register is to be ac cessed during a mrs or emrs cycle. a0 - a12 input address inputs: provide the row address for active commands, and the column address and auto precharge bit for read/write commands, to select one location out of the memory array in the respective bank. a10 is sampled during a precharge command to determine whether the precharge applies to one bank (a10 low) or all banks (a10 high). if only one bank is to be precharged, the bank is selected by ba0, ba1. the address inputs also provide the op-code during a mode register set command. dq input/output data input/output: data bus. dqs input/output data strobe: output with read data, input with write data. edge-aligned with read data, cen- tered in write data. us ed to capture write data. nc no connect: no internal electrical connection is present. v ddq supply dq power supply: 2.6v 0.1v. v ssq supply dq ground v dd supply power supply: 2.6v 0.1v. v ss supply ground v ref supply sstl_2 reference voltage: (v ddq / 2)
hyb25d256[800/160]bt(l)-[5/5a] 256mbit double data rata sdram preliminary ddr400 data sheet addendum 2003-01-10, v0.9 page 5 of 29 block diagram (32mb x 8) receivers 1 dqs ck, ck dll ras cas ck cs we ck control logic column-address counter/latch mode 10 command decode a0-a12, ba0, ba1 cke 15 i/o gating dm mask logic bank0 memory array (8192 x 512x 16) sense amplifiers bank1 bank2 bank3 13 9 1 2 2 refresh counter 8 8 8 input register 1 1 1 1 1 16 16 2 16 clk out data mask data ck, col0 col0 col0 clk in mux dqs generator 8 8 8 8 8 16 dq0-dq7, dm dqs 1 read latch write fifo & drivers note: this functional block diagram is intended to fa cilitate user understanding of the operation of the device; it does not represent an actual circuit implementation. note: dm is a unidirectional signal (input only), but is internally loaded to match the load of the bidi- rectional dq and dqs signals. column decoder 512 (x16) row-address mux registers 13 8192 bank0 row-address latch & decoder 8192 address register drivers bank control logic 13 ck
hyb25d256[800/160]bt(l)-[5/5a] 256mbit double data rata sdram preliminary ddr400 data sheet addendum page 6 of 29 2003-01-10, v0.9 block diagram (16mb x 16) receivers 1 dqs ck, ck dll ras cas ck cs we ck control logic column-address counter/latch mode 9 command decode a0-a11, ba0, ba1 cke 15 i/o gating dm mask logic bank0 memory array (8192 x 256x 32) sense amplifiers bank1 bank2 bank3 13 8 1 2 2 refresh counter 16 16 16 input register 1 1 1 1 1 32 32 2 32 clk out data mask data ck, col0 col0 col0 clk in mux dqs generator 16 16 16 16 16 32 dq0-dq15, dm ldqs, udqs 2 read latch write fifo & drivers note: this functional block diagram is intended to fa cilitate user understanding of the operation of the device; it does not represent an actual circuit implementation. note: udm and ldm are unidirectional signals (input only), but is internally loaded to match the load of the bidirectional dq , udqs and ldqs signals. column decoder 256 (x32) row-address mux registers 13 8192 bank0 row-address latch & decoder 8192 address register drivers bank control logic 13 ck
hyb25d256[800/160]bt(l)-[5/5a] 256mbit double data rata sdram preliminary ddr400 data sheet addendum 2003-01-10, v0.9 page 7 of 29 functional description the 256mb ddr sdram is a high-speed cmos, dynamic random-access memory containing 268, 435, 456 bits. the 256mb ddr sdram is internally configured as a quad-bank dram. the 256mb ddr sdram uses a double-data-rate architec ture to achieve high-speed operation. the double- data-rate architecture is essentially a 2n prefetch architecture, with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the 256mb ddr sdram consists of a single 2n -bit wide, one clock cycle data transfer at the internal dram core and two corresponding n-bit wide, one-half clock cycle data transfers at the i/o pins. read and write accesses to the ddr sdram are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the regis- tration of an active command, which is then followed by a read or write command. the address bits regis- tered coincident with the active command are used to select the bank and row to be accessed (ba0, ba1 select the bank; a0-a12 select the row). the address bits registered coincident with the read or write com- mand are used to select the starting column location for the burst access. prior to normal operation, the ddr sdram must be initialized. the following sections provide detailed infor- mation covering device initialization, register definition, command descriptions and device operation. initialization ddr sdrams must be powered up and initialized in a predefined manner. operat ional procedures other than those specified may result in undefined operation. the following criteria must be met: no power sequencing is specified during power up or power down given the following criteria: v dd and v ddq are driven from a single power converter output and v tt meets the specification and v ref tracks v ddq /2 or the following relationship must be followed: v ddq is driven after or with v dd such that v ddq < v dd + 0.3 v v tt is driven after or with v ddq such that v tt < v ddq + 0.3v v ref is driven after or with v ddq such that v ref < v ddq + 0.3v the dq and dqs outputs are in the high-z state, where they remain until driven in normal operation (by a read access). after all power supply and reference voltages are stable, and the clock is stable, the ddr sdram requires a 200 s delay prior to applying an executable command. once the 200 s delay has been satisfied, a deselect or nop command should be applied, and cke should be brought high. following the nop command, a precharge all command should be applied. next a mode register set command should be issued for the extended mode register, to enable the dll, then a mode register set command should be issued for the mode register, to reset the dll, and to program the operat- ing parameters. 200 clock cycles are required between the dll reset and any executable command. during the 200 cycles of clock for dll locking, a deselect or nop command must be applied. after the 200 clock cycles, a precharge all command should be applied, placing the device in the ?all banks idle? state. once in the idle state, two auto refresh cycles must be performed. additionally, a mode register set command for the mode register, with the reset dll bit deactivated (i.e. to program operating parameters without resetting the dll) must be performed. following these cycles, the ddr sdram is ready for normal operation.
hyb25d256[800/160]bt(l)-[5/5a] 256mbit double data rata sdram preliminary ddr400 data sheet addendum page 8 of 29 2003-01-10, v0.9 register definition mode register the mode register is used to define the specific mode of operation of the ddr sdram. this definition includes the selection of a burst length, a burst type, a cas latency, and an operating mode. the mode reg- ister is programmed via the mode register set command (with ba0 = 0 and ba1 = 0) and retains the stored information until it is programmed again or the device loses power (except for bit a8, which is self-clearing). mode register bits a0-a2 specify the burst length, a3 specifies the type of burst (sequential or interleaved), a4-a6 specify the cas latency, and a7-a12 specify the operating mode. the mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. violating either of these requirements results in unspecified opera- tion. burst length read and write accesses to the ddr sdram are burst oriented, with the burst length being programmable. the burst length determines the maximum number of column locations that can be accessed for a given read or write command. burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types. reserved states should not be used, as unknown operation or incompatibility with future versions may result. when a read or write command is issued, a block of columns equal to the burst length is effectively selected. all accesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary is reached. the block is uniquely selected by a1-ai when the burst length is set to two, by a2-ai when the burst length is set to four and by a3-ai when the burst length is set to eight (where ai is the most significant column address bit for a given configuration). the remaining (least significant) address bit(s) is (are) used to select the starting location within the block. the programmed burst length applies to both read and write bursts.
hyb25d256[800/160]bt(l)-[5/5a] 256mbit double data rata sdram preliminary ddr400 data sheet addendum 2003-01-10, v0.9 page 9 of 29 mode register operation a8 a7 a6 a5 a4 cas latency a3 a2 a1 a0 burst length bt address bus cas latency a6 a5 a4 latency 000 reserved 001 reserved 010 2 0 1 1 3 (optional) 100 reserved 1 0 1 1.5 (optional) 110 2.5 111 reserved burst length a2 a1 a0 burst length 0 0 0 reserved 001 2 010 4 011 8 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved ba1 ba0 a11 a10 a9 0* 0* mode registe r operating mode * ba0 and ba1 must be 0, 0 to select the mode register (vs. the extended mode register). a12 - a9 a8 a7 a6 - a0 operating mode 0 0 0 valid normal operation do not reset dll 0 1 0 valid normal operation in dll reset 001 reserved reserved a3 burst type 0 sequential 1 interleave a12
hyb25d256[800/160]bt(l)-[5/5a] 256mbit double data rata sdram preliminary ddr400 data sheet addendum page 10 of 29 2003-01-10, v0.9 notes: 1. for a burst length of two, a1-ai selects the two-data-element block; a0 selects the first access within the block. 2. for a burst length of four, a2-ai selects the four-data-element block; a0-a1 selects the first access within the block. 3. for a burst length of eight, a3-ai selects the eight-data- element block; a0-a2 selects the first access within the block. 4. whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. burst type accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit a3. the ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in burst definition on page 10. read latency the read latency, or cas latency, is the delay, in clock cycles, between the registration of a read command and the availability of the first burst of output data. the latency can be programmed 2, 2.5 or 3 clocks. cas latency of 1.5 is an optional feature on this device. if a read command is registered at clock edge n, and the latency is m clocks, the data is available nominally coincident with clock edge n + m. reserved states should not be used as unknown operation or incompatibility with future versions may result. burst definition burst length starting column address order of accesses within a burst a2 a1 a0 type = sequential type = interleaved 2 0 0-1 0-1 11-0 1-0 4 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 8 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
hyb25d256[800/160]bt(l)-[5/5a] 256mbit double data rata sdram preliminary ddr400 data sheet addendum 2003-01-10, v0.9 page 11 of 29 operating mode the normal operating mode is selected by issuing a mode register set command with bits a7-a12 set to zero, and bits a0-a6 set to the desired values. a dll reset is initiated by issuing a mode register set com- mand with bits a7 and a9-a12 each set to zero, bit a8 set to one, and bits a0-a6 set to the desired values. a mode register set command issued to reset the dll should always be followed by a mode register set command to select normal operating mode. all other combinations of values for a7-a12 are reserved for future use and/or test modes. test modes and reserved states should not be used as unknown operation or incompatibility with future versions may result. required cas latencies nop nop nop nop nop read cas latency = 2, bl = 4 shown with nominal t ac , t dqsck , and t dqsq . ck ck command dqs dq don?t care cl=2 nop nop nop nop nop read cas latency = 2.5, bl = 4 ck ck command dqs dq cl=2.5
hyb25d256[800/160]bt(l)-[5/5a] 256mbit double data rata sdram preliminary ddr400 data sheet addendum page 12 of 29 2003-01-10, v0.9 extended mode register the extended mode register controls functions beyond those controlled by the mode register; these addi- tional functions include dll enable/disable, and output drive strength selection (optional). these functions are controlled via the bits shown in the extended mode register definition. the extended mode register is programmed via the mode register set command (with ba0 = 1 and ba1 = 0) and retains the stored informa- tion until it is programmed again or the device loses power. the extended mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating any subsequent oper- ation. violating either of these requirements result in unspecified operation. dll enable/disable the dll must be enabled for normal operation. dll enable is required during power up initialization, and upon returning to normal operation after having disabled the dll for the purpose of debug or evaluation. the dll is automatically disabled when entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. any time the dll is enabled, 200 clock cycles must occur before a read command can be issued. this is the reason 200 clock cycles must occur before issuing a read or write command upon exit of self refresh operation. output drive strength the normal drive strength for all outputs is specified to be sstl_2, class ii. in addition this design version supports a weak driver mode for lighter load and/or point-to-point environments which can be activated during mode register set. i-v curves for the normal and weak drive strength are included in this document.
hyb25d256[800/160]bt(l)-[5/5a] 256mbit double data rata sdram preliminary ddr400 data sheet addendum 2003-01-10, v0.9 page 13 of 29 extended mode register definition a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 address bus drive strength a 1 drive strength 0normal 1 weak ba1 ba0 operating mode a 11 a 10 a 9 0 * 1 * * ba0 and ba1 must be 1, 0 to select the extended mode register mode register extended ds dll a 0 dll 0 enable 1 disable an - a3 a2 - a0 operating mode 0 valid normal operation all other states reserved (vs. the base mode register) a 12 0 a 2 0 must be set to 0
hyb25d256[800/160]bt(l)-[5/5a] 256mbit double data rata sdram preliminary ddr400 data sheet addendum page 14 of 29 2003-01-10, v0.9 commands commandsdeselect the deselect function prevents new commands from being executed by the ddr sdram. the ddr sdram is effectively deselected. operations already in progress are not affected. no operation (nop) the no operation (nop) command is used to perfor m a nop to a ddr sdram. this prevents unwanted commands from being registered during idle or wait states. operations already in progress are not affected. mode register set the mode registers are loaded via inputs a0-a12, ba0 and ba1. see mode register descriptions in the reg- ister definition section. the mode register set command can only be issued when all banks are idle and no bursts are in progress. a subsequent executable command cannot be issued until t mrd is met. active the active command is used to open (or activate) a row in a particular bank for a subsequent access. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0-a12 selects the row. this row remains active (or open) for accesses until a precharge (or read or write with auto precharge) is issued to that bank. a precharge (or read or write with auto precharge) command must be issued and com- pleted before opening a different row in the same bank. read the read command is used to initiate a burst read access to an active (open) row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0-ai, aj (where [i = 8, j = don?t care] for x16, [i = 9, j = don?t care] for x8 and [i = 9, j = 11] for x4) selects the starting column location. the value on input a10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed is precharged at the end of the read burst; if auto precharge is not selected, the row remains open for subsequent accesses. write the write command is used to initiate a burst write access to an active (open) row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0-ai, aj (where [i = 9, j = don?t care] for x8; where [i = 9, j = 11] for x4) selects the starting column location. the value on input a10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed is precharged at the end of the write burst; if auto precharge is not selected, the row remains open for subsequent accesses. input data appearing on the dqs is written to the memory array subject to the dm input logic level appearing coin- cident with the data. if a given dm signal is registered low, the corresponding data is written to memory; if the dm signal is registered high, the corresponding data inputs are ignored, and a write is not executed to that byte/column location. precharge the precharge command is used to deactivate (close) the open row in a particular bank or the open row(s) in all banks. the bank(s) will be available for a subsequent row access a specified time (t rp ) after the precharge command is issued. input a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba0, ba1 select the bank. otherwise ba0, ba1 are treated as ?don?t care.? once a bank has been precharged, it is in the idle state and must be activated prior to any
hyb25d256[800/160]bt(l)-[5/5a] 256mbit double data rata sdram preliminary ddr400 data sheet addendum 2003-01-10, v0.9 page 15 of 29 read or write commands being issued to that bank. a precharge command is treated as a nop if there is no open row in that bank, or if the previously open row is already in the process of precharging. auto precharge auto precharge is a feature which performs the same individual-bank precharge functions described above, but without requiring an explicit command. this is accomplished by using a10 to enable auto precharge in conjunction with a specific read or write command. a precharge of the bank/row that is addressed with the read or write command is automatically performed upon completion of the read or write burst. auto pre- charge is nonpersistent in that it is either enabled or disabled for each individual read or write command. auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. the user must not issue another command to the same bank until the precharge (t rp ) is completed. this is determined as if an explicit precharge command was issued at the earliest possible time, as described for each burst type in the operation section of this data sheet. burst terminate the burst terminate command is used to truncate read bursts (with auto precharge disabled). the most re- cently registered read command prior to the burst terminate command is truncated, as shown in the opera- tion section of this data sheet. auto refresh auto refresh is used during normal operation of the ddr sdram and is analogous to cas before ras (cbr) refresh in previous dram types. this command is nonpersistent, so it must be issued each time a refresh is required. the refresh addressing is generated by the internal refresh controller. this makes the address bits ?don?t care? during an auto refresh command. the 256mb ddr sdram requires auto refresh cycles at an aver- age periodic interval of 7.8 s (maximum). to allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. a maximum of eight auto refresh commands can be posted in the system, meaning that the maximum absolute interval between any auto refresh command and the next auto refresh command is 9 * 7.8 s (70.2 s). this maximum absolute interval is short enough to allow for dll updates internal to the ddr sdram to be restricted to auto refresh cycles, without allowing too much drift in t ac between updates. self refresh the self refresh command can be used to retain data in the ddr sdram, even if the rest of the system is powered down. when in the self refresh mode, the ddr sdram retains data without external clocking. the self refresh command is initiated as an auto refresh command coincident with cke transitioning low. the dll is automatically disabled upon entering self refresh, and is automatically enabled upon exiting self refresh (200 clock cycles must then occur before a read command can be issued). input signals except cke (low) are ?don?t care? during self refresh operation. the procedure for exiting self refresh requires a sequence of commands. ck (and ck ) must be stable prior to cke returning high. once cke is high, the sdram must have nop commands issued for t xsnr because time is required for the completion of any internal refresh in progress. a simple algorithm for meeting both refresh and dll requirements is to apply nops for 200 clock cycles before applying any other command.
hyb25d256[800/160]bt(l)-[5/5a] 256mbit double data rata sdram preliminary ddr400 data sheet addendum page 16 of 29 2003-01-10, v0.9 truth table 1a: commands name (function) cs ras cas we address mne notes deselect (nop) h x x x x nop 1, 9 no operation (nop) l h h h x nop 1, 9 active (select bank and activate row) l l h h bank/row act 1, 3 read (select bank and column, and start read burst) l h l h bank/col read 1, 4 write (select bank and column, and start write burst) l h l l bank/col write 1, 4 burst terminate l h h l x bst 1, 8 precharge (deactivate row in b ank or banks) l l h l code pre 1, 5 auto refresh or self refresh (enter self refresh mode) l l l h x ar / sr 1, 6, 7 mode register set l l l l op-code mrs 1, 2 1. cke is high for all commands shown except self refresh. 2. ba0, ba1 select either the base or the extended mode register (ba0 = 0, ba1 = 0 selects mode register; ba0 = 1, ba1 = 0 selects extended mode register; other combinations of ba0-ba1 are reserved; a0-a12 provide the op-code to be written to the selected mode register.) 3. ba0-ba1 provide bank address and a0-a12 provide row address. 4. ba0, ba1 provide bank address; a0-a i provide column address (where i = 8for x16, i = 9 for x8 and 9, 11 for x4); a10 high enables the auto precharge feature (nonpersistent), a10 low disables the auto precharge feature. 5. a10 low: ba0, ba1 determine which bank is precharged. a10 high: all banks are precharged and ba0, ba1 are ?don?t care.? 6. this command is auto refresh if cke is high; self refresh if cke is low. 7. internal refresh counter controls row and bank addressi ng; all inputs and i/os are ?don?t care? except for cke. 8. applies only to read bursts with auto precharge disabled; th is command is undefined (and should not be used) for read bursts with auto precharge enabled or for write bursts 9. deselect and nop are functionally interchangeable. truth table 1b: dm operation name (function) dm dqs notes write enable l valid 1 write inhibit h x 1 1. used to mask write data; provided coincident with the corresponding data.
hyb25d256[800/160]bt(l)-[5/5a] 256mbit double data rata sdram preliminary ddr400 data sheet addendum 2003-01-10, v0.9 page 17 of 29 truth table 2: clock enable (cke) 1. cken is the logic state of cke at clock edge n: cke n-1 was the state of cke at the previous clock edge. 2. current state is the state of the ddr sdram immediately prior to clock edge n. 3. command n is the command registered at clock edge n, and action n is a result of command n. 4. all states and sequences not shown are illegal or reserved. current state cke n-1 cken command n action n notes previous cycle current cycle self refresh l l x maintain self-refresh self refresh l h deselect or nop exit self-refresh 1 power down l l x maintain power-down power down l h deselect or nop exit power-down all banks idle h l deselect or nop precharge power-down entry all banks idle h l auto refresh self refresh entry bank(s) active h l deselect or nop active power-down entry hh see ?truth table 3: current state bank n - command to bank n (same bank)? on page 18 1. deselect or nop commands should be issued on any clock edges occurring during the self refresh exit (t xsnr ) period. a mini- mum of 200 clock cycles are needed before applying a read command to allow the dll to lock to the input clock.
hyb25d256[800/160]bt(l)-[5/5a] 256mbit double data rata sdram preliminary ddr400 data sheet addendum page 18 of 29 2003-01-10, v0.9 truth table 3: current state bank n - command to bank n (same bank) current state cs ras cas we command action notes any h x x x deselect nop. continue previous operation 1-6 l h h h no operation nop. continue previous operation 1-6 idle l l h h active select and activate row 1-6 l l l h auto refresh 1-7 llllmode register set 1-7 row active l h l h read select column and start read burst 1-6, 10 l h l l write select column and start write burst 1-6, 10 l l h l precharge deactivate row in bank(s) 1-6, 8 read (auto precharge disabled) l h l h read select column and start new read burst 1-6, 10 l l h l precharge truncate read burst, start precharge 1-6, 8 l h h l burst terminate burst terminate 1-6, 9 write (auto precharge disabled) l h l h read select column and start read burst 1-6, 10, 11 l h l l write select column and start write burst 1-6, 10 l l h l precharge truncate write burst, start precharge 1-6, 8, 11 1. this table applies when cke n-1 was high and cke n is high (see truth table 2: clock enable (cke) and after t xsnr / t xsrd has been met (if the previous state was self refresh). 2. this table is bank-specific, except where noted, i.e., the cu rrent state is for a specific bank and the commands shown are th ose allowed to be issued to that bank when in that state. exceptions are covered in the notes below. 3. current state definitions: idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. write: a write burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. 4. the following states must not be interrupted by a command issued to the same bank. precharging: starts with registration of a precharge command and ends when t rp is met. once t rp is met, the bank is in the idle state. row activating: starts with registration of an active command and ends when t rcd is met. once t rcd is met, the bank is in the ?row active? state. read w/auto precharge enabled: starts with registration of a read command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank is in the idle state. write w/auto precharge enabled: starts with registration of a write command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank is in the idle state. deselect or nop commands, or allowable commands to the ot her bank should be issued on any clock edge occurring during these states. allowable commands to the other bank are determined by its current state and according truth table 4. 5. the following states must not be interrupted by any executable command; deselect or nop commands must be applied on each positive clock edge during these states. refreshing: starts with registration of an auto refresh command and ends when t rfc is met. once t rfc is met, the ddr sdram is in the ?all banks idle? state. accessing mode register: starts with registration of a mode register set command and ends when t mrd has been met. once t mrd is met, the ddr sdram is in the ?all banks idle? state. precharging all: starts with registrati on of a precharge all command and ends when t rp is met. once t rp is met, all banks is in the idle state. 6. all states and sequences not shown are illegal or reserved. 7. not bank-specific; requires that all banks are idle. 8. may or may not be bank-specific; if all/any banks are to be precharged, all/any must be in a valid state for precharging. 9. not bank-specific; burst terminate affects the most recent read burst, regardless of bank. 10. reads or writes listed in the command/action column include r eads or writes with auto prec harge enabled and reads or writes with auto precharge disabled. 11. requires appropriate dm masking.
hyb25d256[800/160]bt(l)-[5/5a] 256mbit double data rata sdram preliminary ddr400 data sheet addendum 2003-01-10, v0.9 page 19 of 29 truth table 4: current state bank n - command to bank m (different bank) current state cs ras cas we command action notes any h x x x deselect nop/continue previous operation 1-6 l h h h no operation nop/continue previous operation 1-6 idle x x x x any command otherwise allowed to bank m 1-6 row activating, active, or precharging l l h h active select and activate row 1-6 l h l h read select column and start read burst 1-7 l h l l write select column and start write burst 1-7 l l h l precharge 1-6 read (auto precharge disabled) l l h h active select and activate row 1-6 l h l h read select column and start new read burst 1-7 l l h l precharge 1-6 write (auto precharge disabled) l l h h active select and activate row 1-6 l h l h read select column and start read burst 1-8 l h l l write select column and start new write burst 1-7 l l h l precharge 1-6 read (with auto precharge) l l h h active select and activate row 1-6 l h l h read select column and start new read burst 1-7,10 l h l l write select column and start write burst 1-7,9,10 l l h l precharge 1-6 write (with auto precharge) l l h h active select and activate row 1-6 l h l h read select column and start read burst 1-7,10 l h l l write select column and start new write burst 1-7,10 l l h l precharge 1-6 1. this table applies when cke n-1 was high and cke n is high (see truth table 2: clock enable (cke) and after t xsnr / t xsrd has been met (if the previous state was self refresh). 2. this table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands sho wn are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). excep- tions are covered in the notes below. 3. current state definitions: idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. write: a write burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. read with auto precharge enabled: see note 10. write with auto precharge enabled: see note 10. 4. auto refresh and mode register set commands may only be issued when all banks are idle. 5. a burst terminate command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. all states and sequences not shown are illegal or reserved. 7. reads or writes listed in the command/action column include re ads or writes with auto precharge enabled and reads or writes with auto precharge disabled. 8. requires appropriate dm masking. 9. a write command may be applied after the completion of data output. 10. concurrent auto precharge: this device supports ?concurrent auto precharge?. when a read with auto precharge or a write with auto precharge is enabled any command may follow to the other banks as long as that command does not interrupt the read or write data transfer and all other limitations apply (e.g. contention between read data and write data must be avoided). the mimimum delay from a read or write command with auto precharge enable, to a command to a different banks is summarized in table 5.
hyb25d256[800/160]bt(l)-[5/5a] 256mbit double data rata sdram preliminary ddr400 data sheet addendum page 20 of 29 2003-01-10, v0.9 truth table 5: concurrent auto precharge from command to command (different bank) minimum delay with con- current auto precharge support units write w/ap read or read w/ap 1 + (bl/2) + twtr tck write ot write w/ap bl/2 tck precharge or activate 1 tck read w/ap read or read w/ap bl/2 tck write or write w/ap cl (rounded up)+ bl/2 tck precharge or activate 1 tck
hyb25d256[800/160]bt(l)-[5/5a] 256mbit double data rata sdram preliminary ddr400 data sheet addendum 2003-01-10, v0.9 page 21 of 29 simplified state diagram self auto idle mrs emrs row precharge power write power act read a read refs refsx refa ckel mrs ckeh ckeh ckel write power applied automatic sequence command sequence read a write a read pre pre pre pre refresh refresh down power down active on a read a read a write a burst stop preall active precharge precharge preall read write preall = precharge all banks mrs = mode register set emrs = extended mode register set refs = enter self refresh refsx = exit self refresh refa = auto refresh ckel = enter power down ckeh = exit power down act = active write a = write with autoprecharge read a = read with autoprecharge pre = precharge
hyb25d256[800/160]bt(l)-[5/5a] 256mbit double data rata sdram preliminary ddr400 data sheet addendum page 22 of 29 2003-01-10, v0.9 operating conditions input and output capacitances absolute maximum ratings symbol parameter rating units v in , v out voltage on i/o pins relative to v ss 0.5 to v ddq 0.5 v v in voltage on inputs relative to v ss 0.5 to 3.6 v v dd voltage on v dd supply relative to v ss 0.5 to 3.6 v v ddq voltage on v ddq supply relative to v ss 0.5 to 3.6 v t a operating temperature (ambient) 0 to 70 c t stg storage temperature (plastic) 55 to 150 c p d power dissipation 1.0 w i out short circuit output current 50 ma note: stresses greater than those listed under ?absolute maximum ra tings? may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at t hese or any other conditions abov e those indicated in the operat ional sec- tions of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reli ability. parameter package symbol min. max. units notes input capacitance: ck, ck tsop c i1 2.0 3.0 pf 1 delta input capacitance ck, ck tsop c di1 -0.25pf1 input capacitance: all other input-only pins tsop c i2 2.0 3.0 pf 1 delta input capacitance: all other input-only pins tsop c di2 -0.5pf1 input/output capacitance: dq, dqs, dm tsop c io 4.0 5.0 pf 1, 2 delta input/output capacitance : dq, dqs, dm tsop c dio -0.5pf1 1. these values are guarant eed by design and are tested on a sample base only. v ddq = v dd = 2.6v 0.1v, f = 100mhz, t a = 25 c, v out (dc) = v ddq/2 , vout (peak to peak) 0.2v. unused pins are tied to ground . 2. dm inputs are grouped with i/o pins reflecting the fact that they are matched in loading to dq and dqs to facilitate trace ma tching at the board level
hyb25d256[800/160]bt(l)-[5/5a] 256mbit double data rata sdram preliminary ddr400 data sheet addendum 2003-01-10, v0.9 page 23 of 29 electrical characteristics and dc operating conditions (0c t a 70 c; v d dq = 2.6v 0.1v, v dd = 2.6v 0.1v ) symbol parameter min max units notes v dd supply voltage 2.50 2.70 v 1, 2 v ddq i/o supply voltage 2.50 2.70 v 1, 2 v ss , v ssq supply voltage, i/o supply voltage 0 0 v v ref i/o reference voltage v ddq /2-50mv v ddq /2+50mv v 2, 3 v tt i/o termination voltage (system) v ref 0.04 v ref 0.04 v 2, 4 v ih(dc) input high (logic1) voltage v ref 0.15 v ddq 0.3 v 2 v il(dc) input low (logic0) voltage 0.3 v ref 0.15 v 2 v in(dc) input voltage level, ck and ck inputs 0.3 v ddq 0.3 v 2 v id(dc) input differential voltage, ck and ck inputs 0.36 v ddq 0.6 v 2, 5 vi ratio vi-matching pullup current to pulldown current 0.71 1.4 6 i i input leakage current. any input 0v v in v dd (all other pins not under test 0v) 22 a2 i oz output leakage current (dqs are disabled; 0v v out v ddq 55 a2 i oh output high current, normal strength driver (v out 1.95 v) 16.2 ma i ol output low current, normal strength driver (v out 0.35 v) 16.2 ma 1. this is the dc voltage supplied at the dra m and is inclusive all noise up to 10mhz. the dram does not generate any noise that exceeds 150mv above 10mhz and does meet full functionality with up to 150mv above 10mhz at the dram that is generated by the dram itself. any noise above 10mhz at the dram generated from any other source than the dram itself may not exceed the dc voltage range of 2.6v 100mv. the ac and dc tolerances of the data sheet are additive. 2. inputs are not recognized as valid until v ref stabilizes. 3. v ref is expected to be equal to 0.5 v ddq of the transmitting device, and to track variations in the dc level of the same. peak-to-peak noise on v ref may not exceed 2% of the dc value. 4. v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref , and must track variations in the dc level of v ref . 5. v id is the magnitude of the difference between the input level on ck and the input level on ck 6. t he ration of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltage from 0.25 to 1.0v. for a given output, it rep- resents the maximum difference between pullup and pulldown drivers due to process variation.
hyb25d256[800/160]bt(l)-[5/5a] 256mbit double data rata sdram preliminary ddr400 data sheet addendum page 24 of 29 2003-01-10, v0.9 idd specification and conditions (0 c t a 70 c v ddq = 2.5v 0.2v; v dd = 2.5v 0.2v) not es typ. m ax.typ.m ax.typ.m ax.typ.m ax. typ. m ax. 4 x4/x8 70 90 75 100 83 110 85 110 90 115 m a x16 72 95 77 105 86 115 88 115 100 120 m a x4/x8 80 100 90 110 98 120 100 120 105 125 m a x16 83 105 94 115 102 125 104 125 115 135 m a i dd2p 57686869 6 9 m a1, 2 i dd2f 30 35 35 40 35 40 45 55 46 56 m a1, 2 i dd2q 18 22 20 25 20 25 25 28 24 34 m a1, 2 i dd3p 13 16 15 18 15 18 18 21 17 24 m a1, 2 x4/x8 4045505550556065 57 69 m a x16 4250526052606370 60 74 m a x4/x8 79 95 95 115 95 115 110 140 115 145 m a x16 89 110 107 130 107 130 124 160 140 175 m a x4/x8 85 105 105 125 105 125 125 145 125 150 m a x16 96 120 119 140 119 140 141 165 150 180 m a i dd5 126 170 135 180 135 180 144 190 155 195 m a1, 2 standard version 1. 5 2.5 1.5 2.5 1.5 2.5 1.5 2.5 1.6 2.6 m a low power version 1.20 1.25 1.20 1.25 1.20 1.25 1.20 1.25 1.25 1.30 m a x4/x8 150 210 171 225 171 225 208 270 240 280 x16 158 220 180 235 180 235 218 285 260 310 1 . i dd specifications are tested after the device is properly init ialized and m easured at 100 m hz f or ddr200, 133 m hz for ddr266(a) and 166 m hz f or ddr333 2 . i nput sl ew rat e = 1v/ns. 3 . enables on-chip refresh and address counters 4 . test condition for typical values : vdd = 2.5v ,ta = 25c, test condition for m axim um values: test lim it at vdd = 2.7v ,ta = 10c 1, 2 i dd1 operat ing current : one bank; active/read/precharge; burst length 4; refer to the following page for detailed test conditions. precharge floating standby current : /cs >= vih m in, all banks idle; cke >= vi h m in; address and ot her control inputs changing once per clock cycle, vin = vref for dq, dqs and dm . precharge quiet st andby current : /cs >= vih m in, all banks idle; cke >= vi h m in; address and ot her control inputs st able at >= vih m in or <= vil m ax; vi n = vref f or dq, dqs and dm . auto-refresh current : trc = trfc m in, distributed refresh i dd6 self-refresh current : cke <= 0.2v; external clock on i dd7 operat ing current : four bank; four bank interleaving with burst length 4; refer to the following page for detailed test conditions. i dd4r operat ing current : one bank act ive; bl2; reads; continuous burst ; address and control inputs changi ng once per clock cycle; 50% of data outputs changing on every cl ock edge; cl2 for ddr200 and ddr266( a) , cl3 f or ddr333 and ddr400; i out = 0m a i dd3n i dd4w operat ing current : one bank act ive; burst = 2; writes; cont inuous burst; address and control i nputs changing once per clock cycle; 50% of data outputs changi ng on every clock edge; cl2 for ddr200 and ddr266(a), cl3 for ddr333 and ddr400 active standby current : one bank acti ve; cs >= vih m in; cke >= vi h m in; trc = tras m ax; dq, dm , and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle active power-down standby current : one bank active; power-down m ode; cke <= vi l m ax; vi n = vref f or dq, dqs and dm . precharge power-down standby current : all banks idle; power-down m ode; cke <= vi l m ax operat ing current : one bank; active / precharge; trc = trc m in; dq, dm , and dqs inputs changing once per cl ock cycle; address and control inputs changing once every t wo clock cycles 1, 2 i dd0 s ym bol param eter/condition uni t ddr200 -8 ddr266a -7 ddr266 -7f ddr333 -6 ddr400a/b -5 1, 2, 3 m a1, 2 1, 2 1, 2 1, 2
hyb25d256[800/160]bt(l)-[5/5a] 256mbit double data rata sdram preliminary ddr400 data sheet addendum 2003-01-10, v0.9 page 25 of 29 detailed test conditions for ddr sdram idd1 and idd7 idd1 : operating current : one bank operation 1. only one bank is accessed with t rc(min) , burst mode, address and control inputs on nop edge are changing once per clock cycle. l out = 0 ma 2. timing patterns - ddr200 (100mhz, cl=2) : tck = 10 ns, cl=2, bl=4, trcd = 2 * tck, tras = 5 * tck setup: a0 n r0 n n p0 n read : a0 n r0 n n p0 n - repeat the same timing with random address changing 50% of data changing at every burst - ddr266a (133mhz, cl=2) : tck = 7.5 ns, cl=2, bl=4, trcd = 3 * tck, trc = 9 * tck, tras = 5 * tck setup: a0 n n r0 n p0 n n n read : a0 n n r0 n p0 n nn - repeat the same timing with random address changing 50% of data changing at every burst - ddr333 (166mhz, cl=2.5) : tck = 6 ns, cl=2.5, bl=4, trcd = 3 * tck, trc = 9 * tck, tras = 5 * tck setup: a0 n n r0 n p0 n n n read : a0 n n r0 n p0 n n n - repeat the same timing with random address changing 50% of data changing at every burst 3.legend : a=activate, r=read, w=write, p=precharge, n=nop idd7 : operating current: four bank operation 1. four banks are being interleaved with t rc(min) , burst mode, address and control inputs on nop edge are not changing. l out = 0 ma 2. timing patterns - ddr200 (100mhz, cl=2) : tck = 10 ns, cl=2, bl=4, trrd = 2 * tck, trcd= 3 * tck, read with autoprecharge setup: a0 n a1 r0 a2 r1 a3 r2 read : a0 r3 a1 r0 a2 r1 a3 r2- repeat the same timing with random address changing 50% of data changing at every burst - ddr266a (133mhz, cl=2) : tck = 7.5 ns, cl=2, bl=4, trrd = 2 * tck, trcd = 3 * tck setup: a0 n a1 r0 a2 r1 a3 r2 n r3 read : a0 n a1 r0 a2 r1 a3 r2 n r3 - repeat the same timing with random address changing 50% of data changing at every burst - ddr333 (166mhz, cl=2.5) : tck = 6 ns, cl=2.5, bl=4, trrd = 2 * tck, trcd = 3 * tck setup: a0 n a1 r0 a2 r1 a3 r2 n r3 read : a0 n a1 r0 a2 r1 a3 r2 n r3 - repeat the same timing with random address changing 50% of data changing at every burst 3.legend : a=activate, r=read, w=write, p=precharge, n=nop
hyb25d256[800/160]bt(l)-[5/5a] 256mbit double data rata sdram preliminary ddr400 data sheet addendum page 26 of 29 2003-01-10, v0.9 ac characteristics (notes 1-6 apply to the following tables: electrical characteristics and dc operating conditions, ac operating conditions, i dd specifications and conditions, and electrical characteristics and ac timing.) 1. all voltages referenced to v ss . 2. tests for ac timing, i dd , and electrical, ac and dc characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. the figure below represents the timing reference load used in defining the relevant timing parameters of the part. it is not intended to be either a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. system designers will use ibis or other simulation tools to correlate the timing ref- erence load to a system environment. manufacturers will correlate to their production test conditions (generally a coaxial transmission line terminated at the tester electronics). 4. ac timing and i dd tests may use a v il to v ih swing of up to 1.5v in the test environment, but input timing is still refer- enced to v ref (or to the crossing point for ck, ck ), and parameter specifications are guaranteed for the specified ac input levels under normal use conditions. the minimum slew rate for the input signals is 1v/ns in the range between v il(ac) and v ih(ac) . 5. the ac and dc input level specifications are as defined in the sstl_2 standard (i.e. the receiver effectively switches as a result of the signal crossing the ac input level, and remains in that state as long as the signal does not ring back above (below) the dc input low (high) level) 6. for system characteristics like setup & holdtime derating for slew rate, i/o delta rise/fall derating,ddr sdram slew rate standards, overshoot & undershoot specification and clamp v-i characteristics see the latest jedec specification for ddr components ac operating conditions ) ac output load circuit diagram / timing reference load (0 c ta 70 c vddq = 2.6v 0.1v; vdd = 2.6v 0.1v) symbol parameter/condition min max unit notes v ih(ac) input high (logic 1) voltage, dq, dqs, and dm signals v ref + 0.31 v 1, 2 v il(ac) input low (logic 0) voltage, dq, dqs, and dm signals v ref 0.31 v 1, 2 v id(ac) input differential voltage, ck and ck inputs 0.7 v ddq + 0.6 v 1, 2, 3 v ix(ac) input closing point voltage, ck and ck inputs 0.5*v ddq 0.2 0.5*v ddq 0.2 v 1, 2, 4 1. input slew rate = 1v/ns 2. inputs are not recognized as valid until v ref stabilizes. 3. v id is the magnitude of the difference between the input level on ck and the input level on ck . 4. the value of v ix is expected to equal 0.5*v ddq of the transmitting device and must track variations in the dc level of the same. 50 timing reference poin t output (v out ) 30pf v tt
hyb25d256[800/160]bt(l)-[5/5a] 256mbit double data rata sdram preliminary ddr400 data sheet addendum 2003-01-10, v0.9 page 27 of 29 electrical characteristics & ac timing - absolute specifications (0 c t a 70 c v ddq = 2.6v 0.1v; v dd = 2.6v 0.1v) (part 1 of 2) symbol parameter ddr400a -5a ddr400b -5 unit notes min. max. min. max. t ac dq output access time from ck/ck -0.5 +0.5 -0.5 +0.5 ns 1-4 t dqsck dqs output access time from ck/ck -0.55 +0.55 -0.55 +0.55 ns 1-4 t ch ck high-level width 0.45 0.55 0.45 0.55 t ck 1-4 t cl ck low-level width 0.45 0.55 0.45 0.55 t ck 1-4 t hp clock half period min (t cl , t ch )min (t cl , t ch )ns1-4 t ck clock cycle time cl = 3.0 5 10 5 10 ns 1-4 t ck cl = 2.5 5 10 6 10 ns 1-4 t ck cl = 2.0 7.5 10 7.5 10 ns 1-4 t dh dq and dm input hold time 0.40 0.40 ns 1-4 t ds dq and dm input setup time 0.40 0.40 ns 1-4 t ipw control & addr. input pulse width (each input) 2.2 2.2 ns 1-4,10 t dipw dq and dm input pulse width (each input) 1.75 1.75 ns 1-4, 10 t hz data-out high-impedenc e time from ck/ck +0.65 +0.65 ns 1-4, 5 t lz data-out low-impedenc e time from ck/ck -0.65 +0.65 -0.65 +0.65 ns 1-4, 5 t dqss write command to 1st dqs latching transition 0.72 1.28 0.72 1.28 t ck 1-4 t dqsq dqs-dq skew (dqs & associated dq signals) +0.4 +0.4 ns 1-4 t qhs data hold skew factor +0.5 +0.5 ns 1-4 t qh dq output hold time from dqs t hp -t qhs t hp -t qhs ns 1-4 t dqsl,h dqs input low (high) pulse width (write cycle) 0.35 0.35 t ck 1-4 t dss dqs falling edge to ck setup time (write cycle) 0.2 0.2 t ck 1-4 t dsh dqs falling edge hold time from ck (write cycle) 0.2 0.2 t ck 1-4 t mrd mode register set command cycle time 2 2 t ck 1-4 t wpres write preamble setup time 0 0 ns 1-4, 7 t wpst write postamble 0.40 0.60 0.40 0.60 t ck 1-4, 6 t wpre write preamble 0.25 0.25 t ck 1-4 t is address and control input setup time fast slew rate 0.6 0.6 ns 2-4, 10,11 t ih address and control input hold time fast slew rate 0.6 0.6 ns t rpre read preamble 0.9 1.1 0.9 1.1 t ck 1-4 t rpst read postamble 0.40 0.60 0.40 0.60 t ck 1-4 t ras active to precharge command 40 70,000 40 70,000 ns 1-4 t rc active to active/auto-refresh command period 55 55 ns 1-4 t rfc auto-refresh to active/auto-refresh command period 65 65 ns 1-4
hyb25d256[800/160]bt(l)-[5/5a] 256mbit double data rata sdram preliminary ddr400 data sheet addendum page 28 of 29 2003-01-10, v0.9 t rcd active to read or write delay 15 15 ns 1-4 t rp precharge command period 15 15 ns 1-4 t rap active to autoprecharge delay 15 15 ns 1-4 t rrd active bank a to active bank b command 10 10 ns 1-4 t wr write recovery time 15 15 ns 1-4 t dal auto precharge write recovery + precharge time t ck 1-4,9 t wtr internal write to read command delay 1 1 t ck 1-4 t xsnr exit self-refresh to non-read command 75 75 ns 1-4 t xsrd exit self-refresh to read command 200 200 t ck 1-4 t refi average periodic refresh interval (8192 refresh commands per 64ms refresh period) 7.8 7.8 s1-4, 8 1. input slew rate >= 1v/ns for ddr400 2. the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross: the input reference level for signals other than ck/ck , is v ref. ck/ck slew rate are >= 1.0 v/ns 3. inputs are not recognized as valid until v ref stabilizes. 4. the output timing reference level, as measured at the timing reference point indicated in ac characteristics (note 3) is v tt . 5. t hz and t lz transitions occur in the same access time windo ws as valid data transitions. these parameters are not referred to a specific voltage level, but specify when the device is no longer driving (hz), or begins driving (lz). 6. the maximum limit for this parameter is not a device limit. the device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 7. the specific requirement is that dqs be valid (high, low, or some point on a valid transition) on or before this ck edge. a valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previously in progress on the bus, dqs will be transiti oning from hi-z to logic low. if a previous write was in progress, dqs could be high, low, or transitioning from high to low at this time, depending on t dqss . 8. a maximum of eight autorefresh commands can be posted to any given ddr sdram device. 9. for each of the terms, if not already an integer, round to the next highest integer. tck is equal to the actual sys- tem clock cycle time. 10. these parameters guarantee device timing, but they are not necessarilty tested on each device 11. fast slew rate >= 1.0 v/ns , slow slew rate >= 0.5 v/ns and < 1v/ns for command/address and ck & ck slew rate >1.0 v/ns, measured between voh(ac) and vol(ac) electrical characteristics & ac timing - absolute specifications (0 c t a 70 c v ddq = 2.6v 0.1v; v dd = 2.6v 0.1v) (part 2 of 2) symbol parameter ddr400a -5a ddr400b -5 unit notes min. max. min. max.
hyb25d256[800/160]bt(l)-[5/5a] 256mbit double data rata sdram preliminary ddr400 data sheet addendum 2003-01-10, v0.9 page 29 of 29 electrical characteristics & ac timing for ddr400 - applicable specifications expressed in clock cycles (0 c t a 70 c v ddq = 2.6v 0.1v; v dd = 2.6v 0.1v, symbol parameter ddr400a/b units notes min max t mrd mode register set command cycle time 2 t ck 1-54 t wpre write preamble 0.25 t ck 1-5 t ras active to precharge command 8 16000 t ck 1-5 t rc active to active/auto-refresh command period 11 t ck 1-5 t rfc auto-refresh to active/auto-refresh command period 13 t ck 1-5 t rcd active to read or write delay 3 t ck 1-5 t rp precharge command period 3 t ck 1-5 t rrd active bank a to active bank b command 2 t ck 1-5 t wr write recovery time 3 t ck 1-5 t dal auto precharge write recovery + precharge time 5 t ck 1-5 t wtr internal write to read command delay 1 t ck 1-5 t xsnr exit self-refresh to non-read command 10 t ck 1-5 t xsrd exit self-refresh to read command 200 t ck 1-5 1. input slew rate = 1v/ns 2. the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross: the input reference level for signals other than ck/ck , is v ref. 3. inputs are not recognized as valid until v ref stabilizes. 4. the output timing reference level, as measured at the timing reference point indicated in ac characteristics (note 3) is v tt . 5. t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referred to a spe- cific voltage level, but specify when the device is no longer driving (hz), or begins driving (lz).

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